Spectral purity, clock speed, and direct current (dc) power consumption are three key performance parameters of a direct digital synthesizer (DDS). For a given DDS design, improvements in the underlying integrated circuit fabrication process, such as decreasing the delay-power product of the logic family, allow performance improvements without any tradeoff. Unfortunately, making major process improvements takes a considerable amount of resources. For DDSs fabricated in an existing integrated circuit process, however, spectral purity, clock speed and dc power can be traded off against each other for different applications by making architectural or circuit-level design choices. For example, higher speeds can be obtained in exchange for increased dc power by increasing the bias currents. High-speed DDSs, however, have an output spectrum that is dominated by a single large spur, the aliased second-harmonic.
The aliased second-harmonic spur in a DDS can be reduced using dithering techniques. In these techniques, an extra noise source is added to break up discrete spurious signals into broadband noise, thereby increasing the overall noise floor. Additionally, these dithering techniques are only useful for breaking up spurs caused by phase truncation, which is not a significant spur contributor in high-speed DDSs.
It has also been known that a balanced Digital-to-Analog Converter (DAC) results in reduced even-order distortion and provides common-mode rejection to noise. Indeed, a number of DACs have been developed that employ conventional differential amplifiers to maintain a pair of balanced analog signals throughout the DAC to achieve the same advantages. Although a number of differential DACs have been developed by others in the past, they are special DAC designs throughout, typically employing differential amplifiers. In many high speed DDSs, however, single ended DACs are used instead of differential DACs.